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features/benefits ? programmable system clock with prescal er and three different clock sources very low sleep current (< 1 a) very low power consumption in active, power-down and sleep mode 2-kbyte rom, 256 4-bit ram 12 bi-directional i/os up to 6 external/inter nal interrupt sources synchronous serial interface (2-wire, 3-wire) multifunction timer/counter with ? watchdog, por and brown-out function ? voltage monitoring inclusive lo_bat detection ? flash controller atam893 available (sso20) ? code-efficient instruction set ? high-level language programming with qforth compiler 1. description the ata6020n is a member of atmel?s 4-bit single-chip microcontroller family. it con- tains rom, ram, parallel i/o ports, one 8-bit programmable multifunction timer/counter with modulator function, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with external clock input and integrated rc-oscillators. figure 1-1. block diagram voltage monitor external input marc4 utcm osc1 i/o bus rom ram 4-bit cpu core 256 x 4 bit v dd data direction + alternate function data direction + interrupt control port 4 port 5 brown-out protect reset clock management timer 1 watchdog timer timer 2 serial interface port 2 data direction t2o sd sc bp20/nte bp21 bp22 bp23 bp40 int3 sc bp41 vmi t2i bp42 t2o bp43 int3 sd bp50 int6 bp51 int6 bp52 int1 bp53 int1 rc oscillators 2 k x 8 bit vmi with modulator ssi external clock input interval- and 8/12-bit timer t2i v ss low-current microcontroller for watchdog function ata6020n rev. 4708d?4bmcu?09/05
2 4708d?4bmcu?09/05 ata6020n 2. pin configuration figure 2-1. pinning sso20 package ata6020n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 16 vdd bp40/int3/sc bp53/int1 bp52/int1 bp51/int6 bp50/int6 nc osc1 nc nc vss bp43/int3/sd bp42/t2o bp41/vmi/t2i bp23 bp22 bp21 bp20/nte nc nc table 2-1. pin description name type function alternate functi on pin number ss020 reset state vdd ? supply voltage ? 1 na vss ? circuit ground ? 20 na nc ? not connected ? 10 ? nc ? not connected ? 11 ? bp20 i/o bi-directional i/o line of port 2.0 nte test mode enable, see also section ''master reset'' 13 input bp21 i/o bi-directional i/o line of port 2.1 ? 14 input bp22 i/o bi-directional i/o line of port 2.2 ? 15 input bp23 i/o bi-directional i/o line of port 2.3 ? 16 input bp40 i/o bi-directional i/o line of port 4.0 sc serial clock or int3 external interrupt input 2 input bp41 i/o bi-directional i/o line of port 4.1 vmi voltage monitor input or t2i external clock input timer 2 17 input bp42 i/o bi-directional i/o line of port 4.2 t2o timer 2 output 18 input bp43 i/o bi-directional i/o line of port 4.3 sd serial data i/o or int3 external interrupt input 19 input bp50 i/o bi-directional i/o line of port 5.0 int6 external interrupt input 6 input bp51 i/o bi-directional i/o line of port 5.1 int6 external interrupt input 5 input bp52 i/o bi-directional i/o line of port 5.2 int1 external interrupt input 4 input bp53 i/o bi-directional i/o line of port 5.3 int1 external interrupt input 3 input nc ? not connected ? 9 ? nc ? not connected ? 12 ? nc ? not connected ? 7? osc1 i oscillator input external clock input or external trimming resistor input 8 input
3 4708d?4bmcu?09/05 ata6020n 3. introduction the ata6020n is a member of atmel?s 4-bit single-chip microcontroller family. it contains rom, ram, parallel i/o ports, one 8-bit programmable multifunction timer/counter, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with inte- grated rc-oscillators. 4. marc4 architecture general description the marc4 microcontroller consists of an advanced stack-based, 4-bit cpu core and on-chip peripherals. the cpu is based on the harvar d architecture with physically separated pro- gram memory (rom) and data memory (ram). three independent buses, the instruction bus, the memory bus and the i/o bus, are used for parallel communication between rom, ram and peripherals. this enhances program execution sp eed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. the extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and efficient processing of hardware events. the ma rc4 is designed for the high-level programming language qforth. the core includes both, an expr ession and a return stack. this architecture enables high-level language programming without any loss of efficiency or code density. figure 4-1. marc4 core instruction decoder ccr tos alu ram pc rp sp x y program 256 x 4-bit marc4 core clock reset sleep memory bus i/o bus instruction bus reset system clock interrupt controller on-chip peripheral modules memory
4 4708d?4bmcu?09/05 ata6020n 4.1 components of marc4 core the core contains rom, ram, alu, a program counter, ram address registers, an instruction decoder and interrupt controller. the following sections describe each functional block in more detail: 4.1.1 rom the program memory (rom) is mask programmed with the customer application program dur- ing the fabrication of the microcontroller. the rom is addressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 2 kbytes. an additional 1-kbyte of rom exists, which is reserved for quality control self-test software the lowest user rom address segment is taken up by a 512-byte zero page which contains predefined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (scall). the corresponding memory map is shown in figure 4-2 . look-up tables of constants can also be held in rom and are accessed via the marc4's built-in table instruction. figure 4-2. rom map of ata6020n rom (2 k x 8 bit) zero page 7ffh 1ffh 000h 1f0h 1f8h 010h 018h 000h 008h 020h 1e8h 1e0h scall addresses 140h 180h 040h 0c0h 008h $autosleep $r e se t int0 int1 int2 int3 int4 int5 int6 int7 1e0h 1c0h 100h 080h zero page 000h
5 4708d?4bmcu?09/05 ata6020n 4.1.2 ram the ata6020n contains 256 x 4-bit wide static random access memory (ram), which is used for the expression stack. the return stack and data memory are used for variables and arrays. the ram is addressed by any of the four 8- bit wide ram address registers sp, rp, x and y. figure 4-3. ram map 4.1.2.1 expression stack the 4-bit wide expression stack is addressed with the expression stack pointer (sp). all arith- metic, i/o and memory reference operations take their operands, and return their results to the expression stack. the marc4 performs the operati ons with the top of stack items (tos and tos-1). the tos register contains the top elem ent of the expression stack and works in the same way as an accumulator. this stack is also used for passing parameters between subrou- tines and as a scratch pad area for temporary storage of data. 4.1.2.2 return stack the 12-bit wide return stack is addressed by the return stack pointer (rp). it is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. the return stack can also be used as a temporary storage area. the marc4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. the two stacks within the ram have a user definable location and maximum depth. 4.1.3 registers the marc4 controller has seven programmable registers and one condition code register. they are shown in the following programming model. ram fch 00h autosleep ffh 03h 04h x y sp rp tos-1 expression stack return stack global variables ram address register 07h (256 x 4-bit) global variables 4-bit tos tos-1 tos-2 30 sp expression stack return stack 0 11 12-bit rp v
6 4708d?4bmcu?09/05 ata6020n 4.1.3.1 program counter (pc) the program counter is a 12-bit register which contains the address of the next instruction to be fetched from rom. instructions currently being executed are decoded in the instruction decoder to determine the internal micro-operations. f or linear code (no calls or branches) the program counter is incremented with every instruction cycle. if a branch-, call-, return-instruction or an interrupt is executed, the program counter is lo aded with a new address. the program counter is also used with the table instruction to fetch 8-bit wide rom constants. figure 4-4. programming model 4.1.3.2 ram address registers the ram is addressed with the four 8-bit wide ram address registers: sp, rp, x and y. these registers allow access to any of the 256 ram nibbles. 4.1.3.3 expression stack pointer (sp) the stack pointer contains the address of the nex t-to-top 4-bit item (tos-1) of the expression stack. the pointer is automatically pre-increment ed if a nibble is moved onto the stack or post- decremented if a nibble is removed from the stack. every post-decrement operation moves the item (tos-1) to the tos register before the sp is decremented. after a reset, the stack pointer has to be initialized with >sp s0 to allocate the start address of the expression stack area. 4.1.3.4 return stack pointer (rp) the return stack pointer points to the top element of the 12-bit wide return stack. the pointer automatically pre-increments if an element is mov ed onto the stack, or it post-decrements if an element is removed from the stack. the return stack pointer increments and decrements in steps of 4. this means that every time a 12-bit element is stacked, a 4-bit ram location is left unwritten. this location is used by the qforth compiler to allocate 4-bit variables. after a reset the return stack pointer has to be initialized via >rp fch. tos ccr 0 3 0 3 0 7 0 7 7 0 11 rp sp x y pc -- b i program counter return stack pointer expression stack pointer ram address register (x) ram address register (y) top of stack register condition code register carry/borrow branch interrupt enable reserved 0 7 c 0 0 0
7 4708d?4bmcu?09/05 ata6020n 4.1.3.5 ram address registers (x and y) the x and y registers are used to address any 4-bit item in ram. a fetch operation moves the addressed nibble onto the tos. a store operation moves the tos to the addressed ram loca- tion. by using either the pre-increment or post-decrement addressing mode arrays in ram can be compared, filled or moved. 4.1.3.6 top of stack (tos) the top of stack register is the accumulator of the marc4. all arithmetic/logic, memory refer- ence and i/o operations use this register. the to s register receives data from the alu, rom, ram or i/o bus. 4.1.3.7 condition code register (ccr) the 4-bit wide condition code register contains the branch, the carry and the interrupt enable flag. these bits indicate the current state of the cpu. the ccr flags are set or reset by alu operations. the instructions set_bcf, tog_bf, cc r! and di allow direct manipulation of the condition code register. 4.1.3.8 carry/borrow (c) the carry/borrow flag indicates that the borrowing or carrying out of the arithmetic logic unit (alu) occurred during the last arithmetic operation. during shift and rotate operations, this bit is used as a fifth bit. boolean operations have no effect on the c-flag. 4.1.3.9 branch (b) the branch flag controls the conditional program branching. should the branch flag has been set by a previous instruction a conditional branch will cause a jump. this flag is affected by arith- metic, logic, shift, and rotate operations. 4.1.3.10 interrupt enable (i) the interrupt enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. after a reset or on executing the di instruction, the interrupt enable flag is reset thus disabling all in terrupts. the core will not accept any further interrupt requests until the interrupt enable flag ha s been set again by either executing an ei or sleep instruction.
8 4708d?4bmcu?09/05 ata6020n 4.1.4 alu the 4-bit alu performs all the arithmetic, logical, shift and rotate operations with the top two ele- ments of the expression stack (tos and tos-1) and returns the result to the tos. the alu operations affects the carry/borrow and branch flag in the condition code register (ccr). figure 4-5. alu zero-address operations 4.1.5 i/o bus the i/o ports and the registers of the peripheral modules are i/o mapped. all communication between the core and the on-chip peripherals take place via the i/o bus and the associated i/o control. with the marc4 in and out instructions, the i/o bus allows a direct read or write access to one of the 16 primary i/o addresses. more about the i/o access to the on-chip periph- erals is described in the section ?peripheral modules? on page 20 . the i/o bus is internal and is not accessible by the customer on the final microcontroller device, but it is used as the interface for the marc4 emulation (see section ?emulation?). 4.1.6 instruction set the marc4 instruction set is optimized for the high level programming language qforth. many marc4 instructions are qforth words. this enables the compiler to generate a fast and compact program code. the cpu has an instruction pipeline allowing the controller to prefetch an instruction from rom at the same time as the present instruction is being executed. the marc4 is a zero address machine, the instructions containing only the operation to be per- formed and no source or destination address fields. the operations are implicitly performed on the data placed on the stack. there are one- and two-byte instructions which are executed within 1 to 4 machine cycles. a marc4 machine cycle is made up of two system clock cycles (syscl). most of the instructions are only one byte long and are executed in a single machine cycle. for more information refer to the ?marc4 programmer?s guide?. 4.1.7 interrupt structure the marc4 can handle interrupts with eight different priority levels. they can be generated from the internal and external interrupt sources or by a software interrupt from the cpu itself. each interrupt level has a hard-wired priority and an associated vector for the service routine in rom (see table 4-1 on page 10 ). the programmer can postpone the processing of interrupts by resetting the interrupt enable flag (i ) in the ccr. an interrupt oc currence will still be registered, but the interrupt routine only starts after the i-flag is set. all interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module (see section ?peripheral modules? on page 20 ). tos-1 ccr ram tos-2 sp tos-3 tos alu tos-4
9 4708d?4bmcu?09/05 ata6020n figure 4-6. interrupt handling 4.1.7.1 interrupt processing in order to process the eight interrupt levels, th e marc4 includes an interrupt controller with two 8-bit wide interrupt pending and interrupt active registers. the interrupt controller samples all interrupt requests during every non-i/o instruction cycle and latches these in the interrupt pend- ing register. if no higher priority interrupt is present in the interrupt active register, it signals the cpu to interrupt the current program execution. if the interrupt enable bit is set, the processor enters an interrupt ackn owledge cycle. during this cycle a shor t call (scall) instruction to the service routine is executed and the current pc is saved on the return stack. an interrupt service routine is completed with the rti instruction. this instruction resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the pro- gram counter. when the interrupt enable flag is reset (triggering of interrupt routines are disabled), the execution of new interrupt service routines is inhibited but not the logging of the interrupt requests in the interrupt pending register. the execution of the interrupt is delayed until the interrupt enable flag is set again. note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). it should be noted that automatic stacking of the rbr is not carried out by the hardware and so if rom banking is used, the rbr must be st acked on the expression stack by the application program and restored before the rti. after a master reset (power-on, brown-out or watchdog reset), the interrupt enable flag and the interrupt pending and interrupt active register are all reset. 7 6 5 4 3 2 1 0 priority level int5 active int7 active int2 pending swi0 int2 active int0 pending int0 active int2 rti rti int5 int3 active int3 rti rti rti int7 time main / autosleep main / autosleep
10 4708d?4bmcu?09/05 ata6020n 4.1.7.2 interrupt latency the interrupt latency is the time from the occurrence of the interrupt to the interrupt service rou- tine being activated. this is extremely short (t aking between 3 to 5 machine cycles depending on the state of the core). 4.1.7.3 software interrupts the programmer can generate interrupts by using the software interrupt instruction (swi), which is supported in qforth by predefined macros named swi0...swi7. the software triggered interrupt operates exactly like any hardware tri ggered interrupt. the swi instruction takes the top two elements from the expression stack and writes the corresponding bits via the i/o bus to the interrupt pending register. therefore, by using the swi instruction, interrupts can be re-prior- itized or lower priority processes scheduled for later execution. 4.1.7.4 hardware interrupts in the ata6020n, there are eleven hardware interrupt sources with seven different levels. each source can be masked individually by mask bits in the corresponding control registers. an over- view of the possible hardware configurations is shown in table 4-2 on page 10 . table 4-1. interrupt priority table interrupt priority rom addres s interrupt opcode function int0 lowest 040h c8h (scall 040h) software interrupt (swi0) int1 | 080h d0h (scall 080h) external hardware interrupt, any edge at bp52 or bp53 int2 | 0c0h d8h (scall 0c0h) timer 1 interrupt int3 | 100h e8h (scall 100h) ssi interrupt or external hardware interrupt at bp40 or bp43 int4 | 140h e8h (scall 140h) timer 2 interrupt int5 | 180h f0h (scall 180h) software interrupt (sw15) int6 1c0h f8h (scall 1c0h) external hardware interrupt, at any edge at bp50 or bp51 int7 highest 1e0h fch (scall 1e0h) voltage monitor (vm) interrupt table 4-2. hardware interrupts interrupt interrupt mask interrupt source register bit int1 p5cr p52m1, p52m2 p53m1, p53m2 any edge at bp52 any edge at bp53 int2 t1m t1im timer 1 int3 sisc sim ssi buffer full/empty or bp40/bp43 interrupt int4 t2cm t2im timer 2 compare match/overflow int6 p5cr p50m1, p50m2 p51m1, p51m2 any edge at bp50 any edge at bp51 int7 vcm vim external/internal voltage monitoring
11 4708d?4bmcu?09/05 ata6020n 4.2 master reset the master reset forces the cpu into a well-defined condition. it is unmaskable and is activated independent of the current program state. it can be triggered by either initial supply power-up, a short collapse of the power supply, the brown-out de tection circuitry, a watchdog time-out, or an external input clock supervisor stage (see figure 4-7 ). a master reset activation will reset the interrupt enable flag, the interrupt pending register and the interrupt active register. during the power-on reset phase, the i/o bus control signals are set to reset mode, thereby, initializing all on-chip peripherals. all bi-directional ports are set to input mode. attention: during any reset phase, the bp20/ nte input is driven towards v dd by an additional internal strong pull-up transistor. this pin must not be pulled down to v ss during reset by any external circuitry representing a resistor of less than 150 k ? . releasing the reset results in a short ca ll instruction (opcode c1h) to the rom address 008h. this activates the initialization routine $reset which in turn has to initialize all necessary ram variables, stack pointers and peripheral configuration registers. figure 4-7. reset configuration 4.2.1 power-on reset and brown-out detection the ata6020n has a fully integrated power-on reset and brown-out detection circuitry. for reset generation no external components are needed. these circuits ensure that the core is held in the reset state until the minimum operating supply voltage has been reached. a reset condition will also be generated should the supply voltage drop momentarily below the minimum operating le vel except when a power-down mode is acti- vated (the core is in sleep mode and the peripheral clock is stopped). in this power-down mode the brown-out detection is disabled. two values for the brown-out voltage threshold are programmable via the bot bit in the sc-register. reset timer v dd cl power-on reset internal reset res cl=syscl/4 v dd v ss brown-out detection v dd v ss watch- dog cwd res ext. clock supervisor exin pull-up nrst reset timer v dd cl power-on reset internal reset res cl=syscl/4 v dd v ss brown-out detection watch- dog cwd res ext. clock supervisor exin pull-up nrst v dd v ss
12 4708d?4bmcu?09/05 ata6020n a power-on reset pulse is generated by a v dd rise across the default bot voltage level (3.0 v). a brown-out reset pulse is generated when v dd falls below the brown-out voltage threshold. two values for the brown-out voltage threshold are programmable via the bot-bit in the sc-register. when the controller runs in the upper supply voltage range with a high system clock frequency, the high threshold must be used. when it runs with a lower system clock frequency, the low threshold and a wider supply voltage range may be chosen. for further details, see the electrical specification and the sc-register description for bot programming. figure 4-8. brown-out detection bot = 1, low brown-out voltage threshold. (3.0v is the reset value). bot = 0, high brown-out voltage threshold (4.0v). 4.2.2 watchdog reset the watchdog's function can be enabled at the wd c-register and triggers a reset with every watchdog counter overflow. to suppress the watchdog reset, the watchdog counter must be regularly reset by reading the watchdog register address (cwd). the cpu reacts in exactly the same manner as a reset stimulus from any of the above sources. 4.2.3 external clock supervisor the external input clock supervisor function can be enabled if the external input clock is selected within the cm- and sc-registers of the clock module. the cpu reacts in exactly the same man- ner as a reset stimulus from any of the above sources. v dd cpu reset t bot = 1 4.0 v 3.0 v cpu reset bot = 0 t d t d = 1.5 ms (typically) t d t d
13 4708d?4bmcu?09/05 ata6020n 4.3 voltage monitor the voltage monitor consists of a comparator with internal voltage reference. it is used to super- vise the supply voltage or an external voltage at the vmi pin. the comparator for the supply voltage has two internal programmable threshol ds: one lower threshold (4.0v) and one higher threshold (5.0v). for external voltages at the vmi pin, the comparator threshold is set to v bg = 1.25v. the vms-bit indicates if the superv ised voltage is below (vms = 0) or above (vms = 1) this threshold. an interrupt can be generated when the vms-bit is set or reset to detect a rising or falling slope. a voltage monitor interrupt (int7) is enabled when the interrupt mask bit (vim) is reset in the vmc-register. figure 4-9. voltage monitor 4.3.1 voltage monitor control/status register vm2 : v oltage monitor m ode bit 2 vm1 : v oltage monitor m ode bit 1 vm0 : v oltage monitor m ode bit 0 v dd vm2 voltage monitor vm1 vm0 vim vms - - res out in bp41/ vmi int7 vmc vmst primary register address: ?f?hex bit 3 bit 2 bit 1 bit 0 vmc: write vm2 vm1 vm0 vim reset value: 1111b vmst: read ? ? reserved vms reset value: xx11b
14 4708d?4bmcu?09/05 ata6020n vim v oltage i nterrupt m ask bit vim = 0, voltage monitor interrupt is enabled vim = 1, voltage monitor interrupt is disabled vms v oltage m onitor s tatus bit vms = 0, the voltage at the comparator input is below v ref vms = 1, the voltage at the comparator input is above v ref figure 4-10. internal supply voltage supervisor figure 4-11. external input voltage supervisor table 4-3. voltage monitor modes vm2 vm1 vm0 function 1 1 1 disable voltage monitor 110 external (vim input), internal refere nce threshold (1.25v), interrupt with negative slope 101not allowed 100 external (vmi input), internal refere nce threshold (1.25v), interrupt with positive slope 0 1 1 internal (supply voltage), high threshold (5.0v), interrupt with negative slope 010not allowed 0 0 1 internal (supply voltage), low threshol d (4.0v), interrupt with negative slope 000not allowed v dd low threshold high threshold vms = 1 low threshold high threshold vms = 0 5.0 v 4.0 v 1.25 v vmi vms = 1 vms = 0 positive slope negative slope vms = 1 vms = 0 interrupt negative slope interrupt positive slope internal reference level t
15 4708d?4bmcu?09/05 ata6020n 4.4 clock generation 4.4.1 clock module the ata6020n contains a clock module with two different internal rc-oscillator types. osc1 can be used as input for external clocks or to connect an external trimming resistor for rc-oscil- lator 2. all necessary circuitry, except the tr imming resistor, is integrated on-chip. one of these oscillator types or an external input clock can be selected to generate the system clock (syscl). in applications that do not require exact timing, it is possible to use the fully integrated rc-oscil- lator 1 without any external co mponents. the rc-oscillator 1 ce nter frequency tolerance is better than 50%. rc-oscillator 2 is a trimmable oscillator where by the oscillator frequency can be trimmed with an external resistor attached between osc1 and gnd. in this configuration, rc-oscillator 2 frequency can be maintained stable to within a tolerance of 15% over the full operating temperature and voltage range. the clock module is programmable via software with the clock management register (cm) and the system configuration register (sc). the requir ed oscillator configurati on can be selected with the os1-bit and the os0-bit in the sc-register. a programmable 4-bit divider stage allows the adjustment of the system clock speed. a special feature of the clock management is that an external oscillator may be used and switched on and off via a port pin for the po wer-down mode. before the external clock is switc hed off, the internal rc-oscillato r 1 must be selected with the ccs-bit and then the sleep mode may be activated. in this state an interrupt can wake up the controller with the rc-oscillator, and the external oscillator can be activated and selected by software. a synchronization stage avoids clock periods that are too short if the clock source or the clock speed is changed. if an external input clock is selected, a supervisor circuit monitors the external input and generates a hardware reset if the external clock source fails or drops below 500 khz for more than 1 ms. figure 4-12. clock module ext. clock exin exout stop rc oscillator2 rcout2 stop r trim oscin rc oscillator 1 rcout1 control stop in1 in2 cin /2 /2 /2 /2 divider sleep wdl osc-stop nstop ccs css1 css0 cm bot - - - os1 os0 subcl syscl sc osc1 cin/16
16 4708d?4bmcu?09/05 ata6020n the clock module gene rates two output clocks. one is th e system clock (syscl) and the other the periphery (subcl). the sysc l can supply the core and th e peripherals and the subcl can supply only the peripherals with clocks. the modes for clock sources are programmable with the os1-bit and os0-bit in the sc-register and the ccs-bit in the cm-register. 4.4.2 oscillator circuits and external clock input stage the ata6020n consists of two di fferent internal rc-o scillators and one external clock input stage. 4.4.2.1 rc-oscillator 1 fully integrated for timing insensitive applications, it is possible to use the fully integrated rc-oscillator 1. it operates without any external comp onents and saves additional co sts. the rc-oscillator 1 cen- ter frequency tolerance is better than 50% over the full temperature and voltage range. the basic center frequency of the rc-oscillator 1 is f o 4.0 mhz the rc-oscillator 1 is selected by default after power-on reset. figure 4-13. rc-oscillator 1 4.4.2.2 external input clock the osc1 can be driven by an external clock source provided it meets the specified duty cycle, rise and fall times and input levels. additionally, the external clock stage contains a supervisory circuit for the input clock. t he supervisor function is controll ed via the os1, os0-bit in the sc-register and the ccs-bit in the cm-register. if the external input clock fails and ccs = 0 is set in the cm-register, the supervisory circuit generates a hardware reset. the input clock has failed if the frequency is less than 500 khz for more than 1 ms. table 4-4. clock modes mode os1 os0 clock source for syscl clock source for subcl ccs = 1 ccs = 0 111 rc-oscillator 1 (internal) external input clock c in /16 201 rc-oscillator 1 (internal) rc-oscillator 2 with external trimming resistor c in /16 rc-oscillator 1 rcout1 stop control rcout1 osc-stop
17 4708d?4bmcu?09/05 ata6020n figure 4-14. external input clock 4.4.2.3 rc-oscillator 2 with external trimming resistor the rc-oscillator 2 is a high re solution trimmable oscillator wher eby the oscillator frequency can be trimmed with an external resistor between osc1 and v dd . in this configuration, the rc-oscil- lator 2 frequency can be maintained stable to within a tolerance of 10% over the full operating temperature and voltage range from v dd = 3.5v to 5.5v. for example: an output frequency at the rc-oscillator 2 of 1.6 mhz, can be obtained by con- necting a resistor r ext = 47 k ? (see figure 4-15 ). figure 4-15. rc-oscillator 2 table 4-5. supervisor function control bits os1 os0 ccs supervisor reset output (res) 1 1 0 enable 1 1 1 disable x 0 x disable ext. input clock exout stop ext. clock rcout1 osc-stop exin ccs res osc1 clock monitor rc-oscillator 2 rcout2 stop rcout2 osc-stop r trim osc1 r ext
18 4708d?4bmcu?09/05 ata6020n 4.4.3 clock management the clock management register controls the syst em clock divider and sy nchronization stage. writing to this register trig gers the synchronization cycle. 4.4.3.1 clock management register (cm) 4.4.3.2 system configuration register (sc) auxiliary register address: ?3?hex bit 3bit 2bit 1bit 0 cm nstop ccs css1 css0 reset value: 1111b nstop n ot stop peripheral clock nstop = 0, stops the peripheral cl ock while the core is in sleep mode nstop = 1, enables the peripheral cl ock while the core is in sleep mode ccs c ore c lock s elect ccs = 1, the internal rc-oscillator 1 generates syscl ccs = 0, an external clock source or the rc-oscillator 2 with the external resistor at osc1 generates syscl dependent on the setting of os0 and os1 in the system configuration register css1 c ore s peed s elect 1 css0 c ore s peed s elect 0 table 4-6. core speed select css1 css0 divider note 0016? 1 1 8 reset value 104? 012? primary register address: ?3?hex bit 3bit 2bit 1bit 0 sc: write bot ? os1 os0 reset value: 1x11b bot b rown- o ut t hreshold bot = 1, low brown-out voltage threshold (3.0 v) bot = 0, high brown-out voltage threshold (4.0 v) os1 o scillator s elect 1 os0 o scillator s elect 0
19 4708d?4bmcu?09/05 ata6020n note: if bit ccs = 0 in the cm-register, the rc-oscillator 1 always stops. 4.5 power-down modes the sleep mode is a shut-down condition which is used to reduce the average system power consumption in applications wher e the microcontroller is not fully utilized. in this mode, the sys- tem clock is stopped . the sleep mode is entered via the sl eep instruction. this instruction sets the interrupt enable bit (i) in the condition code register to enable all interrupts and stops the core. during the sleep mode the peripheral modules remain active and are able to generate interrupts. the microcontroller exits the sleep mode by carrying out any interrupt or a reset. the sleep mode can only be kept when none of th e interrupt pending or active register bits are set. the application of the $autosleep rout ine ensures the correct function of the sleep mode. the total power consumption is directly proportional to the active time of the microcontroller. for a rough estimation of the expected average system current consumption, the following formula should be used: i total (v dd ,f syscl ) = i sleep + (i dd t active /t total ) i dd depends on v dd and f syscl the ata6020n has various power-down modes. during the sleep mode the clock for the marc4 core is stopped. with the nstop-bit in the clock management register (cm), it is pro- grammable if the clock for the on-chip peripherals is active or stopped during the sleep mode. if the clock for the core and the peripherals is stopped the selected osc illator is sw itched off. note: 1. osc-stop = sleep and nstop and wdl table 4-7. oscillator select mode os1 os0 input for subcl selected oscillators 111 c in /16 rc-oscillator 1 and external input clock 201 c in /16 rc-oscillator 1 and rc-oscillator 2 table 4-8. power-down modes mode cpu core osc-stop (1) brown-out function rc-oscillator 1 rc-oscillator 2 external input clock active run no active run yes power-down sleep no active run yes sleep sleep yes stop stop stop
20 4708d?4bmcu?09/05 ata6020n 5. peripheral modules 5.1 addressing peripherals accessing the peripheral modules takes place via the i/o bus (see figure 5-1 ). the in or out instructions allow direct addressing of up to 16 i/o modules. a dual register addressing scheme has been adopted to enable direct addressing of the primary register. to address the auxiliary register, the access must be switched with an au xiliary switching module. thus, a single in (or out) to the module address will re ad (or write into) the modules primary register. accessing the auxiliary register is performed with the same instruction preceded by writing the module address into the auxiliary switching module. byte wide registers are accessed by multiple in (or out) instructions. for more complex peripheral modules, with a larger number of registers, extended addressing is used. in this case, a bank of up to 16 subport registers are indirectly addressed with the subport address. the first out-instruction writes the subport address to the sub-address register, the second in or out instruction reads data from or writes data to the addressed subport. figure 5-1. example of i/o addressing subaddress reg. subport fh i/o bus aux. reg. bank of primary regs. primary reg. (address pointer) auxiliary switch module indirect subport access to other modules 1 2 (subport register write) 3 4 5 1 2 3 6 6 4 5 example of qforth program code 1 2 4 5 3 6 addr. (asw) = auxililiary switch module address 1 2 2 1 2 2 4 5 5 (auxiliary register write) module asw module m1 module m2 module m3 subport eh primary reg. primary reg. subport 1 subport 0 dual register access single register access addr. (sport) addr. (m1) out sport_data addr. (m1) out (subport register read) addr. (sport) addr. (m1) out addr. (m1) in (subport register write byte) addr. (sport) addr. (m1) out sport_data (lo) addr. (m1) out sport_data (hi) addr. (m1) out (subport register read byte) addr. (sport) addr. (m1) out addr. (m1) in (hi) addr. (m1) in (lo) (primary register write) prim._data addr. (m2) out addr. (m2) addr. (asw) out aux._data addr. (m2) out (primary register read) addr. (m2) in (auxiliary register read ) addr. (m2) addr. (asw) out addr. (m2) in (auxiliary register write byte) addr. (m2) addr. (asw) out aux._data (lo) addr. (m2) out aux._data (hi) addr. (m2) out (primary register write) prim._data addr. (m3) out (primary register read) addr. (m3) in addr. (mx) = module mx address addr. (sport) = subport address prim._data = data to be written into primary register aux._data = data to be written into auxiliary register aux._data (lo) = data to be written into auxiliary register (low nibble) aux._data (hi) = data to be written into auxiliary register (high nibble) sport_data (lo) = data to be written into subport (low nibble) sport_data (hi) = data to be written into subport (high nibble) (lo) = sport_data (low nibble) (hi) = sport_data (high nibble)
21 4708d?4bmcu?09/05 ata6020n table 5-1. peripheral addresses port address name write/read reset value register function module type see page 2 p2dat w/r 1111b port 2 - data register/pin data m2 23 aux. p2cr w 1111b port 2 - control register 23 3 sc w 1x11b port 3 - system configuration register m3 18 cwd r xxxxb watchdog reset m3 12 aux. cm w 1111b port 3 - clock management register m2 18 4 p4dat w/r 1111b port 4 - data register/pin data m2 26 aux. p4cr w 1111 1111b port 4 - control register (byte) 26 5 p5dat w/r 1111b port 5 - data register/pin data m2 25 aux. p5cr w 1111 1111b port 5 - control register (byte) 25 6? reserved 7 t12sub w ? data to timer 1/2 subport m1 20 support address 0 t2c w 0000b timer 2 control register m1 38 1 t2m1 w 1111b timer 2 mode register 1 m1 38 2 t2m2 w 1111b timer 2 mode register 2 m1 40 3 t2cm w 0000b timer 2 compare mode register m1 41 4 t2co1 w 1111b timer 2 compare register 1 m1 41 5 t2co2 w 1111 1111b timer 2 compare register 2 (byte) m1 41 6? ? ?reserved 7? ? ?reserved 8 t1c1 w 1111b timer 1 control register 1 m1 29 9 t1c2 w x111b timer 1 control register 2 m1 30 a wdc w 1111b watchdog control register m1 30 b-f reserved 8 asw w 1111b auxiliary/switch register asw 20 9 stb w xxxx xxxxb serial transmit buffer (byte) m2 51 srb r xxxx xxxxb serial receive buffer (byte) 51 aux. sic1 w 1111b serial interface control register 1 49 a sisc w/r 1x11b serial interface status/control register m2 51 aux. sic2 w 1111b serial interface control register 2 50 b? reserved c? reserved d rbr w 0000b rom bank switch register m3 7 e? ?reserved f vmc w 1111b voltage monitor control register m3 13 vmst r xx11b voltage monitor status register m3 13
22 4708d?4bmcu?09/05 ata6020n 5.2 bi-directional ports ports 2, 4 and 5 are 4 bits wide. all ports may be used for data input or output. all ports are equipped with schmitt trigger inputs and a variety of mask options for open-drain, open-source, full-complementary outputs, pull-up and pull-down transistors. all port data registers (pxdat) are i/o mapped to the primary address register of the respective port address and the port con- trol register (pxcr) , to the corres ponding auxiliary register. there are three different directional ports available: port 2 4-bit wide bitwise-programmable i/o port. port 5 4-bit wide bitwise-programmable bi-d irectional port with optional static pull-ups and programmable interrupt logic. port 4 4-bit wide bitwise-programmable bi-d irectional port also provides the i/o interface to timer 2, ssi, voltage moni tor input and external interrupt input. 5.2.1 bi-directional port 2 this, and all other bi-directional ports include a bitwise-programmable control register (p2cr), which enables the indivi dual programming of each port bit as input or output. it also opens up the possibility of reading the pin c ondition when in output mode. this is a usef ul feature for self- testing and for serial bus applications. port 2, however, has an increased drive ca pability and an additi onal low resistance pull-up/-down transistor mask option. care should be taken connecting external components to bp20/nte. during any reset phase, the bp20/nte input is driven towards v dd by an additional internal strong pull-up transistor. this pin must not be pulled down (active or passive) to v ss during reset by any external circuitry rep- resenting a resistor of less than 150 k ? . this prevents the circuit from unintended switching to test mode enable through the application circuitr y at pin bp20/nte. resistors less than 150 k ? might lead to an undefined state of the internal test logic thus disabling the application firmware. to avoid any conflict with the optional internal pull-down transistors, bp20 handles the pull-down options in a different way than all other ports. bp20 is the only port that switches off the pull- down transistors during reset. figure 5-2. bi-directional port 2 master reset q q bp2y (1) mask options (1) p2daty p2cry i/o bus d i/o bus i/o bus pull-up pull-down v dd static pull-up (data out) (direction) s d s v dd static pull-down (1) (1) (1) (1) (1)
23 4708d?4bmcu?09/05 ata6020n 5.2.1.1 port 2 data register (p2dat) bit 3 = msb, bit 0 = lsb 5.2.1.2 port 2 control register (p2cr) value: 1111b means all pins in input mode 5.2.2 bi-directional port 5 this, and all other bi-directional ports include a bitwise-programmable control register (p5cr), which allows individual programming of each port bi t as input or output. it also opens up the pos- sibility of reading the pin condition when in output mode. this is a useful feature for self testing and for serial bus applications. the port pins can also be used as external interrupt inputs (see figure 5-3 on page 24 and fig- ure 5-4 on page 24 ). the interrupts (int1 and int6) can be masked or independently configured to trigger on either edge. the interrupt configuration and port direction is controlled by the port 5 control register (p5cr). an additional low resistance pull-up/-down transistor mask option pro- vides an internal bus pull-up for serial bus applications. the port 5 data register (p5dat) is i/o mapped to the primary address register of address '5'h and the port 5 control register (p5cr) to the co rresponding auxiliary register. the p5cr is a byte-wide register and is configured by writing first the low nibble then the high nibble (see sec- tion ?addressing peripherals? on page 20 ). primary register address: ?2?hex bit 3 bit 2 bit 1 bit 0 p2dat p2dat3 p2dat2 p2dat1 p2dat0 reset value: 1111b auxiliary register address: ?2?hex bit 3 bit 2 bit 1 bit 0 p2cr p2cr3 p2cr2 p2cr1 p2cr0 reset value: 1111b table 5-2. port 2 control register code 3 2 1 0 function x x x 1 bp20 in input mode x x x 0 bp20 in output mode x x 1 x bp21 in input mode x x 0 x bp21 in output mode x 1 x x bp22 in input mode x 0 x x bp22 in output mode 1 x x x bp23 in input mode 0 x x x bp23 in output mode
24 4708d?4bmcu?09/05 ata6020n figure 5-3. bi-directional port 5 figure 5-4. port 5 external interrupts master reset q v dd bp5y (1) mask options p5daty i/o bus d in enable i/o bus pull-up pull-down (1) static pull-up (data out) s v dd v dd v dd (1) (1) (1) (1) (1) static pull-down data in in_enable bp53 p53m2 p53m1 p52m2 p52m1 p51m2 p51m1 p50m2 p50m1 decoder decoder decoder decoder bi-directional port data in in_enable bp52 i/o-bus data in in_enable bp51 i/o-bus data in in_enable bp50 int1 int6 p5cr bi-directional port bi-directional port bi-directional port
25 4708d?4bmcu?09/05 ata6020n 5.2.2.1 port 5 data register (p5dat) 5.2.2.2 port 5 control register (p5cr) byte write p5xm2, p5xm1 ? port 5x interrupt mode/direction code 5.2.3 bi-directional port 4 the bi-directional port 4 is both a bitwise config urable i/o port and provides the external pins for the timer 2, ssi and the voltage monitor input (vmi). as a normal port, it performs in exactly the same way as bi-directional port 2 (see figure 5-2 on page 22 ). two additional multiplexes allow data and port direction control to be passed over to other internal modules (timer 2, vm or ssi). the i/o-pins for the sc and sd lines have an additional mode to generate an ssi-interrupt. all four port 4 pins can be individually switched by the p4cr-register. figure 5-5 on page 26 shows the internal interfaces to bi-directional port 4. primary register address:?5?hex bit 3 bit 2 bit 1 bit 0 p5dat p5dat3 p5dat2 p5dat1 p5dat0 reset value: 1111b auxiliary register address:?5?hex bit 3 bit 2 bit 1 bit 0 p5cr first write cycle p51m2 p51m1 p50m2 p50m1 reset value: 1111b bit 7 bit 6 bit 5 bit 4 second write cycle p53m2 p53m1 p52m2 p52m1 reset value: 1111b table 5-3. port 5 control register auxiliary address:?5?hex first write cycle second write cycle code 3 2 1 0 function code 3 2 1 0 function x x 1 1 bp50 in input mode - interrupt disabled x x 1 1 bp52 in input mode ? interrupt disabled x x 0 1 bp50 in input mode - rising edge interrupt x x 0 1 bp52 in input mode ? rising edge interrupt x x 1 0 bp50 in input mode - falling edge interrupt x x 1 0 bp52 in input mode ? falling edge interrupt x x 0 0 bp50 in output mode - interrupt disabled x x 0 0 bp52 in output mode ? interrupt disabled 1 1 x x bp51 in input mode - interrupt disabled 1 1 x x bp53 in input mode ? interrupt disabled 0 1 x x bp51 in input mode - rising edge interrupt 0 1 x x bp53 in input mode ? rising edge interrupt 1 0 x x bp51 in input mode - falling edge interrupt 1 0 x x bp53 in input mode ? falling edge interrupt 0 0 x x bp51 in output mode - interrupt disabled 0 0 x x bp53 in output mode ? interrupt disabled
26 4708d?4bmcu?09/05 ata6020n figure 5-5. bi-directional port 4 5.2.3.1 port 4 data register (p4dat) 5.2.3.2 port 4 control register (p4cr) byte write p4xm2, p4xm1 ? port 4x interrupt mode/direction code master reset q v dd bpxy (1) mask options (1) pxdaty i/o bus d i/o bus i/o bus pull-up pull-down s pxcry s q d pxmry pout (direction) pdir intx pin static pull-up v dd v dd static pull-down (1) (1) (1) (1) (1) primary register address: ?4?hex bit 3 bit 2 bit 1 bit 0 p4dat p4dat3 p4dat2 p4dat1 p4dat0 reset value: 1111b auxiliary register address: ?4?hex bit 3 bit 2 bit 1 bit 0 p4cr first write cycle p41m2 p41m1 p40m2 p40m1 reset value: 1111b bit 7 bit 6 bit 5 bit 4 second write cycle p43m2 p43m1 p 42m2 p42m1 reset value: 1111b table 5-4. port 4 control register auxiliary address: ?4?hex first write cycle second write cycle code 3 2 1 0 function code 3 2 1 0 function x x 1 1 bp40 in input mode x x 1 1 bp42 in input mode x x 1 0 bp40 in output mode x x 1 0 bp42 in output mode x x 0 1 bp40 enable alternate function (sc for ssi) x x 0 x bp42 enable alternate function (t2o for timer 2) x x 0 0 bp40 enable alternate function (falling edge interrupt input for int3) 1 1 x x bp43 in input mode 1 1 x x bp41 in input mode 1 0 x x bp43 in output mode 1 0 x x bp41 in output mode 0 1 x x bp43 enable alternate function (sd for ssi) 0 1 x x bp41 enable alternate function (vmi for voltage monitor input) 0 0 x x bp43 enable alternate function (falling edge interrupt input for int3) 0 0 x x bp41 enable alternate function (t2i external clock input for timer 2) ??
27 4708d?4bmcu?09/05 ata6020n 5.2.4 universal timer/counter/ communication module (utcm) the universal timer/counter/communication module (utcm) consists of timer 1, timer 2 and a synchronous serial interface (ssi). timer 1 is an interval timer that can be used to generate periodical interrupts and as prescaler for timer 2, the serial interface and the watchdog function. timer 2 is an 8/12-bit timer with an external clock input (t2i) and an output (t2o). the ssi operates as a two-wire serial interface or as a shift register for modulation. the modulator units work together with the timers and shift the data bits out of the shift register. there is a multitude of modes in which the timers and the serial interface can work together. figure 5-6. utcm block diagram 5.2.5 timer 1 timer 1 is an interval timer which can be used to generate periodic interrupts and as a prescaler for timer 2, timer 3, the serial interface and the watchdog function. timer 1 consists of a programmabl e 14-stage divider that is dri ven by either subcl or syscl. the timer output signal can be used as a prescaler clock or as subcl and as source for the timer 1 interrupt. because of other system requ irements timer 1 output t1out is synchronized with syscl. therefore, in the power-down mode sleep (cpu core -> sleep and osc-stop -> yes) the output t1out is sto pped (t1out = 0). nevertheless, timer 1 can be active in sleep and generate timer 1 interrupts. the interrupt is maskable via the t1im bit and the subcl can be bypassed via the t1bp bit of the t1c2 register . the time interval for the timer output can be programmed via the timer 1 control register t1c1. this timer starts running automatically after any power-on reset! if the watchdog function is not activated, the timer can be restarted by writing into the t1c1 register with t1rm = 1. mux watchdog interval/prescaler timer 1 modu- lator 2 4-bit counter 2/1 compare 2/1 mux mux dcg 8-bit counter 2/2 compare 2/2 control timer 2 mux 8-bit shift-register receive-buffer transmit-buffer control ssi scl int4 int2 nrst int3 pout tog2 t1out subcl syscl from clock module t2i t2o sc sd i/o bus
28 4708d?4bmcu?09/05 ata6020n timer 1 can also be used as a watchdog timer to prevent a system from stalling. the watchdog timer is a 3-bit counter that is supplied by a separate output of timer 1. it generates a system reset when the 3-bit counter overflows. to avoid th is, the 3-bit counter must be reset before it overflows. the application software has to accomplish this by reading the cwd register. after power-on reset the watchdog must be activated by software in the $reset initialization routine. there are two watchdog modes, in one mode the watchdog can be switched on and off by software, in the other mode the watchdog is active and locked. this mode can only be stopped by carrying out a system reset. the watchdog timer operation mode and the time interval for the watchdog reset can be pro- grammed via the watchdog control register (wdc). figure 5-7. timer 1 module figure 5-8. timer 1 and watchdog 14-bit prescaler cl1 4-bit watchdog mux wdcl t1im t1bp t1mux nrst int2 t1out t1cs syscl subcl q5 q1 q2 q3 q4 q6 q8 q8 q11 q11 q14 q14 res cl decoder watchdog mode control mux for interval timer decoder mux for watchdog timer t1rm t1c2 t1c1 t1c0 3 2 wdl wdr wdt1 wdt0 wdc res t1mux subcl t1bp t1im t1im=0 t1im=1 int2 t1out t1c2 reset (nrst) watchdog divider/8 divider reset t1c1 write of the t1c1 register cl1 wdcl read of the cwd register
29 4708d?4bmcu?09/05 ata6020n 5.2.5.1 timer 1 control register 1 (t1c1) bit 3 = msb, bit 0 = lsb the three bits t1c[2:0] select the divider for timer 1. the resulting time interval depends on this divider and the timer 1 input clock source. the ti mer input can be supplie d by the system clock or via clock management. if the clock management generates the subcl, the selected input clock from the rc osc illator or an external clock is divided by 16 note: tin: input clock period = 1/cin (see figure 4-12 on page 15 ) address: '7'hex ? subaddress: '8'hex bit 3 bit 2 bit 1 bit 0 t1c1 t1rm t1c2 t1c1 t1c0 reset value: 1111b t1rm t imer 1 r estart m ode t1rm = 0, write access without timer 1 restart t1rm = 1, write access with timer 1 restart note: if wdl = 0, timer 1 restart is impossible t1c2 t imer 1 c ontrol bit 2 t1c1 t imer 1 c ontrol bit 1 t1c0 t imer 1 c ontrol bit 0 table 5-5. timer 1 control bits t1c2 t1c1 t1c0 divider time interval with subcl from clock management time interval with syscl = 2/1 mhz 000 2 tin 32 1 s/2 s 001 4 tin 64 2 s/4 s 010 8 tin 128 4 s/8 s 0 1 1 16 tin 256 8 s/16 s 1 0 0 32 tin 512 16 s/32 s 101256 tin 4096 128 s/256 s 1102048 tin 32768 1024 s/2048 s 1 1 1 16384 tin 262144 8192 s/16384 s
30 4708d?4bmcu?09/05 ata6020n 5.2.5.2 timer 1 control register 2 (t1c2) bit 3 = msb, bit 0 = lsb 5.2.5.3 watchdog control register (wdc) bit 3 = msb, bit 0 = lsb both these bits control the time interval for the watchdog reset note: t in : input clock period = 1/c in (see figure 4-12 on page 15 ) address: '7'hex ? subaddress: '9'hex bit 3 bit 2 bit 1 bit 0 t1c2 ? t1bp t1cs t1im reset value: x111b t1bp t imer 1 subcl b y p assed t1bp = 1, tiout = t1mux t1bp = 0, t1out = subcl t1cs t imer 1 input c lock s elect t1cs = 1, cl1 = subcl (see figure 5-11 on page 33 ) t1cs = 0, cl1 = syscl (see figure 5-11 on page 33 ) t1im t imer 1 i nterrupt m ask t1im = 1, disables timer 1 interrupt t1im = 0, enables timer 1 interrupt address: ?7?hex ? subaddress: ?a?hex bit 3 bit 2 bit 1 bit 0 wdc wdl wdr wdt1 wdt0 reset value: 1111b wdl w atch d og l ock mode wdl = 1, the watchdog can be enabled and disabled by using the wdr-bit wdl = 0, the watchdog is enabled and locked. in this mode the wdr-bit has no effect. after the wdl- bit is cleared, the watchdo g is active until a system reset or power-on reset occurs. wdr w atch d og r un and stop mode wdr = 1, the watchdog is stopped/disabled wdr = 0, the watchdog is active/enabled wdt1 w atch d og t ime 1 wdt0 w atch d og t ime 0 table 5-6. watchdog time control bits wdt1 wdt0 divider delay time to reset with t in = 1/(2/1 mhz) 0 0 512 0.256 ms/0.512 ms 0 1 2048 1.024 ms/2.048 ms 1 0 16384 8.2 ms/16.4 ms 1 1 131072 65.5 ms/131 ms
31 4708d?4bmcu?09/05 ata6020n 5.2.6 timer 2 8-/12 bit timer for: interrupt, square-wave, pulse and duty cycle generation baud rate generation for the internal shift register manchester and bi-phase modulation together with the ssi carrier frequency generation and modulation together with the ssi timer 2 can be used as an interval timer for interr upt generation, as signal generator or as baud rate generator and modulator for the serial interface. it consists of a 4-bit and an 8-bit up counter stage which both have compare registers. the 4-bit counter stages of timer 2 are cascadable as a 12-bit timer or as an 8-bit timer with a 4-bi t prescaler. the timer can also be configured as an 8-bit timer and a separate 4-bit prescaler. the timer 2 input can be supplied via the system clock, the external input clock (t2i), the timer 1 output clock or the shift clock of the serial interface. the external input clock t2i is not syn- chronized with syscl. ther efore, it is possible to use timer 2 with a higher cloc k speed than syscl. furthermore; with that input clock timer 2 operates in the power-down mode sleep (cpu core -> sleep and osc-stop -> yes) as well as in the power-down (cpu core -> sleep and osc-stop -> no). all other clock sources supplied no clock signal in sleep. the 4-bit counter stages of timer 2 have an additional clock output (pout). its output has a modulator stage that allows the generation of pulses as well as the generation and modulation of carrier frequencies. timer 2 output can modulate with the shift register inter- nal data output to generate bi-phase- or manchester-code. if the serial interface is used to modulate a bit-stream, the 4-bit stage of timer 2 has a special task. the shift register can only handle bit-stream lengths divisible by 8. for other lengths, the 4-bit counter stage can be used to stop the mo dulator after the right bit-count is shifted out. if the timer is used for carrier frequency modulati on, the 4-bit stage works together with an addi- tional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier frequency and duty cycle. the 8-bit counter is used to enable and disable the modulator output for a programmable count of pulses. the timer has a 4-bit and an 8-bit compare register for programming the time interval, t. for pro- gramming the timer function, it has four mode and control registers. the comparator output of stage 2 is controlled by a special compare mode register (t2cm). this register contains mask bits for the actions (counter reset, output toggle, timer interrupt) which can be triggered by a compare match event or the counter overflow. this architecture enables the timer function for various modes. timer 2 compare data values. timer 2 has a 4-bit compare register (t2co1) and an 8-bit compare register (t2co2). both these compare registers are cascadable as a 12-bit compare register, or 8-bit compare register and 4-bit compare register. for 12-bit compare data value: m = x +1 0 x 4095 for 8-bit compare data value: n = y +1 0 y 255 for 4-bit compare data value: i = z +1 0 z 15
32 4708d?4bmcu?09/05 ata6020n figure 5-9. timer 2 5.2.6.1 timer 2 modes mode 1: 12-bit compare counter the 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. a compare match signal of the 4-bit and the 8-bit stage generates the signal for the counter reset, toggle flip-flop or interrupt. the compare action is programmable via the compare mode register (t2cm). the 4- bit counter overflow (ovf1) supp lies the clock output (pout) with clocks. the duty cycle gener- ator (dcg) has to be bypassed in this mode. figure 5-10. 12-bit compare counter 4-bit counter 2/1 res ovf1 compare 2/1 t2co1 cm1 pout ssi pout cl2/2 dcg t2m1 p4cr 8-bit counter 2/2 res ovf2 compare 2/2 t2co2 t2cm control tog2 int4 bi-phase manchester modulator output mout m2 to modulator 3 t2o timer 2 modulator output-stage t2m2 so control ssi ssi i/o-bus t2c cl2/1 t2i syscl t1out scl i/o-bus dcgo 4-bit counter 4-bit compare res 4-bit register cm1 pout (cl2/1 /16) 8-bit counter 8-bit compare 8-bit register ovf2 cm2 res t2rm t2otm timer 2 output mode and t2otm-bit t2im t2ctm tog2 int4 cl2/1 dcg t2d1, 0
33 4708d?4bmcu?09/05 ata6020n mode 2: 8-bit compare counter with 4-bit programmable prescaler the 4-bit stage is used as a programmable prescaler for the 8-bit counter stage. in this mode, a duty cycle stage is also available. this stage can be used as an additional 2-bit prescaler or for generating duty cycles of 25%, 33% and 50%. t he 4-bit compare output (cm1) supplies the clock output (pout) with clocks. figure 5-11. 8-bit compare counter mode 3/4: 8-bit compare counter and 4-bit programmable prescaler in these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit prescaler and an 8-bit timer with a 2-bit prescaler or as a duty cycle generator. only in mode 3 and mode 4 can the 8-bit counter be supplied via the external clock input (t2i) which is selected via the p4cr register. the 4-bit prescaler is started by activating mode 3 and stopped and reset in mode 4. changing mode 3 and 4 has no effect for the 8-bit timer stage. the 4-bit stage can be used as a prescaler for the ssi or to generate the stop signal for modulator 2. figure 5-12. 4-/8-bit compare counter 4-bit counter 4-bit compare res 4-bit register cm1 pout 8-bit counter 8-bit compare 8-bit register ovf2 cm2 res t2rm t2otm timer 2 output mode and t2otm-bit t2im t2ctm tog2 int4 cl2/1 dcg t2d1, 0 dcgo 4-bit counter 4-bit compare res 4-bit register 8-bit counter 8-bit compare 8-bit register ovf2 cm2 res t2rm t2otm timer 2 output mode and t2otm-bit t2im t2ctm tog2 int4 cl2/2 dcg t2d1, 0 dcgo p41m2, 1 p4cr cm1 pout cl2/1 mux t1out syscl scl t2cs1, 0 syscl t2i
34 4708d?4bmcu?09/05 ata6020n 5.2.6.2 timer 2 output modes the signal at the timer output is generated via modulator 2. in the toggle mode, the compare match event toggles the output t2o. for high re solution duty cycle modulat ion 8 bits or 12 bits can be used to toggle the ou tput. in the duty cycle burst m odulator modes the dcg output is connected to t2o and switched on and off either by the toggle flipflop output or the serial data line of the ssi. modulator 2 also has 2 modes to output the content of the serial interface as bi- phase or manchester code. the modulator output stage can be configured by the output control bits in the t2m2 register. the modulator is started with the start of the shift register (sir = 0) and stopped either by carry- ing out a shift register stop (sir = 1) or compare match event of stage 1 (cm1) of timer 2. for this task, timer 2 mode 3 must be used and the prescaler has to be supplied with the internal shift clock (scl). figure 5-13. timer 2 modulator output stage 5.2.6.3 timer 2 output signals timer 2 output mode 1 toggle mode a : a timer 2 compare match toggles the output flip-flop (m2) -> t2o figure 5-14. interrupt timer/square wave generator ? output toggles with each edge com- pare match event toggle res/set bi-phase/ manchester modulator t2top t2os2, 1, 0 t2m2 t2o m2 m2 s1 s2 s3 re fe omsk ssi control tog2 so dcgo 4 000123 4 0123 4 0123 01 input counter 2 t2r counter 2 cmx int4 t2o
35 4708d?4bmcu?09/05 ata6020n toggle mode b : a timer 2 compare match toggles the output flip-flop (m2) -> t2o figure 5-15. pulse generator ? timer output toggles with timer start if t2ts-bit is set timer 2 output mode 1 toggle mode c : a timer 2 compare match toggles the output flip-flop (m2) -> t2o figure 5-16. pulse generator ? timer toggles with timer overflow and compare match 4 000123 567 4 0123 56 input counter 2 t2r counter 2 cmx int4 t2o toggle by start t2o 4095/ 255 4 000123 567 4 0123 56 input counter 2 t2r counter 2 cmx ovf2 int4 t2o 4095/ 255
36 4708d?4bmcu?09/05 ata6020n timer 2 output mode 2 duty cycle burst generator 1: the dcg output signal (dcgo) is given to the output, and gated by the output flip-flop (m2) figure 5-17. carrier frequency burst modulation with timer 2 toggle flip-flop output timer 2 output mode 3 duty cycle burst generator 2: the dcg output signal (dcgo) is given to the output, and gated by the ssi internal data output (so) figure 5-18. carrier frequency burst modulation with ssi data output timer 2 output mode 4 bi-phase modulator: timer 2 modulates the ssi internal data output (so) to bi-phase code. figure 5-19. bi-phase modulation 1 2012012345012012345678012345678910012345 dcgo counter 2 tog2 m2 t2o counter = compare register (=2) 1 201201201201201201201201201201201201201 dcgo counter 2 tog2 so t2o counter = compare register (=2) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 tog2 sc so t2o 000 0 0011 0101 11 1 1 8-bit sr-data bit 7 bit 0 data: 00110101
37 4708d?4bmcu?09/05 ata6020n timer 2 output mode 5 manchester modulator: timer 2 modulates the ssi internal data output (so) to manchester code. figure 5-20. manchester modulation timer 2 output mode 7 pwm mode: pulse-width modulation output on timer 2 output pin (t2o) in this mode the timer overflow defines the period and the compare register defines the duty cycle. during one period only the first compare ma tch occurrence is used to toggle the timer out- put flip-flop, until overflow occur all further compare match are ignored. this avoids the situation that changing the compare register causes the occurrence of several compare match during one period. the resolution at the pulse-width modulation timer 2 mode 1 is 12-bit and all other timer 2 modes are 8-bit. figure 5-21. pwm modulation 5.2.6.4 timer 2 registers timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function. all registers are indirectly addressed using extended addressing as described in section ?addressing peripherals? on page 20 . the alternate functions of the ports bp41 or bp42 must be selected with the port 4 control register p4cr, if one of the timer 2 modes require an input at t2i/bp41 or an output at t2o/bp42. tog2 sc so t2o 00 0 0011 0101 11 1 1 8-bit sr-data bit 7 bit 0 0 bit 7 bit 0 data: 00110101 0 0 50 255 100 0 255 0 150 255 0 50 255 0 100 t2r input clock counter 2/2 counter 2/2 ovf2 cm2 int4 t2o load the next compare value t2co2=150 load load t1 t2 t3 t1 t2 tt t t t
38 4708d?4bmcu?09/05 ata6020n 5.2.6.5 timer 2 control register (t2c) 5.2.6.6 timer 2 mode register 1 (t2m1) address: ?7?hex ? subaddress: ?0?hex bit 3bit 2bit 1bit 0 t2c t2cs1 t2cs0 t2ts t2r reset value: 0000b t2cs1 t imer 2 c lock s elect bit 1 t2cs0 t imer 2 c lock s elect bit 0 table 5-7. timer 2 clock select bits t2cs1 t2cs0 input clock (cl 2/1) of counter stage 2/1 0 0 system clock (syscl) 0 1 output signal of timer 1 (t1out) 1 0 internal shift clock of ssi (scl) 11reserved t2ts t imer 2 t oggle with s tart t2ts = 0, the output flip?flop of timer 2 is not toggled with the timer start t2ts = 1, the output flip?flop of timer 2 is toggled when the timer is started with t2r t2r t imer 2 r un t2r = 0, timer 2 stop and reset t2r = 1, timer 2 run address: ?7?hex ? subaddress: ?1?hex bit 3 bit 2 bit 1 bit 0 t2m1 t2d1 t2d0 t2ms1 t2ms0 reset value: 1111b t2d1 t imer 2 d uty cycle bit 1 t2d0 t imer 2 d uty cycle bit 0 table 5-8. timer 2 duty cycle bits t2d1 t2d0 function of duty cycle generator (dcg) additional divider effect 1 1 bypassed (dcgo0) /1 1 0 duty cycle 1/1 (dcgo1) /2 0 1 duty cycle 1/2 (dcgo2) /3 t2ms1 t imer 2 m ode s elect bit 1 t2ms0 t imer 2 m ode s elect bit 0
39 4708d?4bmcu?09/05 ata6020n 5.2.6.7 duty cycle generator the duty cycle generator generates duty cycles from 25%, 33% or 50%. the frequency at the duty cycle generator output depends on the duty cycle and the timer 2 prescaler setting. the dcg-stage can also be used as an additional programmable prescaler for timer 2. figure 5-22. dcg output signals table 5-9. timer 2 mode select bits mode t2ms1 t2ms0 clock output (pout) timer 2 modes 1 1 1 4-bit counter overflow (ovf1) 12-bit compare counter, the dcg have to be bypassed in this mode 2 1 0 4-bit compare output (cm1) 8-bit compare counter with 4-bit programmable prescaler and duty cycle generator 3 0 1 4-bit compare output (cm1) 8-bit compare counter clocked by syscl or the external clock input t2i, 4-bit prescaler run, the counter 2/1 starts after writing mode 3 4 0 0 4-bit compare output (cm1) 8-bit compare counter clocked by syscl or the external clock input t2i, 4-bit prescaler stop and resets dcgin dcgo0 dcgo1 dcgo2 dcgo3
40 4708d?4bmcu?09/05 ata6020n 5.2.6.8 timer 2 mode register 2 (t2m2) note: if one of these output modes is used the t2o al ternate function of port 4 must also be activated. 5.2.6.9 timer 2 compare and compare mode registers timer 2 has two separate compare registers, t2co1 for the 4-bit stage and t2co2 for the 8-bit stage of timer 2. the timer compares the contents of the compare register current counter value and if it matches it generates an output signal. de pending on the timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop as ssi clock or as a clock for the next counter stage. in the 12-bit timer mode, t2co1 contains bits 0 to 3 and t2co2 bits 4 to 11 of the 12-bit com- pare value. in all other modes, the two compare registers work independently as a 4-bit and 8-bit compare register. when assigned to the compare register a co mpare event will be suppressed. address: ?7?hex ? subaddress: ?2?hex bit 3 bit 2 bit 1 bit 0 t2m2 t2top t2os2 t2os1 t2os0 reset value: 1111b t2top t imer 2 t oggle o utput p reset this bit allows the programmer to preset the timer 2 output t2o. t2top = 0, resets the toggle outputs with the write cycle (m2 = 0) t2top = 1, sets toggle outputs with the write cycle (m2 = 1) note: if t2r = 1, no output preset is possible t2os2 t imer 2 o utput s elect bit 2 t2os1 t imer 2 o utput s elect bit 1 t2os0 t imer 2 o utput s elect bit 0 table 5-10. timer 2 output select bits output mode t2os2 t2ms1 t2ms0 clock output (pout) 1111 toggle mode: a timer 2 compare match toggles the output flip-flop (m2) -> t2o 2110 duty cycle burst genera tor 1: the dcg output signal (dcg0) is given to the output and gated by the output flip-flop (m2) 3101 duty cycle burst genera tor 2: the dcg output signal (dcgo) is given to the output and gated by the ssi internal data output (so) 4100 bi-phase modulator: timer 2 modulates the ssi internal data output (so) to bi-phase code 5011 manchester modulator: timer 2 modulates the ssi internal data output (so) to manchester code 6010 ssi output: t2o is used directly as ssi internal data output (so) 7001pwm mode: an 8/12-bit pwm mode 8000not allowed
41 4708d?4bmcu?09/05 ata6020n 5.2.6.10 timer 2 compare mode register (t2cm) 5.2.6.11 timer 2 compare register 1 (t2co1) in prescaler mode the clock is bypassed if the compare register t2co1 contains 0. 5.2.6.12 timer 2 compare register 2 (t2co2) byte write address: ?7?hex ? subaddress: ?3?hex bit 3 bit 2 bit 1 bit 0 t2cm t2otm t2ctm t2rm t2im reset value: 0000b t2otm t imer 2 o verflow t oggle m ask bit t2otm = 0, disable overflow toggle t2otm = 1, enable overflow toggle, a c ounter overflow (ovf2) toggles the output flip-flop (tog2). if the t2otm-bit is set, only a counter overflow can generate an interrupt except on the timer 2 output mode 7. t2ctm t imer 2 c ompare t oggle m ask bit t2ctm = 0, disable compare toggle t2ctm = 1, enable compare toggle, a match of the counter with the compare register toggles output flip-flop (tog2). in timer 2 output mode 7 and when the t2ctm- bit is set, only a matc h of the counter with the compare register can generate an interrupt. t2rm t imer 2 r eset m ask bit t2rm = 0, disable counter reset t2rm = 1, enable counter reset, a match of the counter with the compare register resets the counter t2im t imer 2 i nterrupt m ask bit t2im = 0, disable timer 2 interrupt t2im = 1, enable timer 2 interrupt table 5-11. timer 2 toggle mask bits timer 2 output mode t2otm t2ctm timer 2 interrupt source 1, 2, 3, 4, 5 and 6 0 x compare match (cm2) 1, 2, 3, 4, 5 and 6 1 x overflow (ovf2) 7 x 1 compare match (cm2) address: ?7?hex ? subaddress: ?4?hex t2co1 write cycle bit 3 bit 2 bit 1 bit 0 reset value: 1111b address: ?7?hex ? subaddress: ?5?hex t2co2 first write cycle bit 3 bit 2 bit 1 bit 0 reset value: 1111b second write cycle bit 7 bit 6 bit 5 bit 4 reset value: 1111b
42 4708d?4bmcu?09/05 ata6020n 5.2.7 synchronous serial interface (ssi) 5.2.7.1 ssi features ? 2- and 3-wire nrz ?2-wire mode with timer 2: ? bi-phase modulation ? manchester modulation ? pulse-width demodulation ? burst modulation 5.2.7.2 ssi peripheral configuration the synchronous serial interface (ssi) can be used either for serial communication with external devices such as eeproms, shift registers, display drivers, ot her microcontrollers, or as a means for generating and capturing on-chip serial streams of data. external data communication takes place via port 4?s (bp4) multi-functional port which can be software configured by writing the appropriate control word into the p4cr register. the ssi can be configured in any one of the following ways: 1. 2-wire external interface for bi-directional data communication with one data terminal and one shift clock. the ssi uses port bp43 as a bi-directional serial data line (sd) and bp40 as a shift clock line (sc). 2. 3-wire external interface for simultaneous input and output of serial data, with a serial input data terminal (si), a serial output data terminal (so) and a shift clock (sc). the ssi uses bp40 as a shift clock (sc), while the serial data input (si) is applied to bp43 (configured in p4cr as input). serial output data (so) in this case is passed through to bp42 (configured in p4cr to t2o) via timer 2 output stage (t2m2 configured in mode 6). 3. timer/ssi combined modes ? the ssi used together with timer 2 is capable of per- forming a variety of data modulation and functions (see section ?timer 1? on page 27 ). the modulating data is converted by the ssi into a continuous serial stream of data which is in turn modulated in one of the timer functional blocks. figure 5-23. block diagram of the synchronous serial interface 8-bit shift register msb lsb shift_cl so sic1 sic2 sisc sc control stb srb si timer 2 output int3 sc i/o-bus i/o-bus ssi-control tog2 pout t1out syscl so si sd transmit buffer receive buffer sci /2
43 4708d?4bmcu?09/05 ata6020n 5.2.7.3 general ssi operation the ssi is comprised essentially of an 8?bit shift register with two associated 8-bit buffers - the receive buffer (srb) for capturing the incoming se rial data and a transmit buffer (stb) for inter- mediate storage of data to be serially output. both buffers are directly accessable by software. transferring the parallel buffer data into and out of the shift register is controlled automatically by the ssi control, so that both single byte transfers or continuous bit streams can be supported. the ssi can generate the shift clock (sc) either from one of several on-chip clock sources or accept an external clock. the external shift clock is output on, or applied to the port bp40. selection of an external clock source is perfor med by the serial clo ck direction control bit (scd). in the combinational modes, the required clock is selected by the corresponding timer mode. the ssi can operate in three data transfer modes ? synchronous 8-bit shift mode, a 9-bit multi- chip link mode (mcl), containing 8-bit dat a and 1-bit acknowledge, and a corresponding 8-bit mcl mode without acknowledge. in both mcl mo des the data transmission begins after a valid start condition and ends with a valid stop condition. external ssi clocking is not supported in these modes. the ssi should thus generate and have full control over the shift clock so that it can always be regarded as an mcl-bus master device. all directional control of the external data port used by the ssi is handled automatically and is dependent on the transmission direction set by the serial data direction (sdd) control bit. this control bit defines whether the ssi is currently operating in transmit (tx) mode or receive (rx) mode. serial data is organized in 8-bit telegrams which ar e shifted with the most significant bit first. in the 9-bit mcl mode, an additional acknowledge bit is appended to the end of the telegram for handshaking purposes (see ?mcl protocol?). at the beginning of every telegram, the ssi control loads the transmit buffer into the shift register and proceeds immediately to shift data serially ou t. at the same time, incoming data is shifted into the shift register input. this incoming data is automatically loaded into the receive buffer when the complete telegram has been received. data can, if required thus be simultaneously received and transmitted. before data can be transferred, the ssi must first be activated. this is performed by means of the ssi reset control (sir) bit. all further operation then depends on the data directional mode (tx/rx) and the present status of the ssi buffer registers shown by the serial interface ready status flag (srdy). this srdy flag indicates the (empty/full) status of either the transmit buffer (in tx mode), or the receive buffer (in rx mode). the control logic ensures that data shifting is temporarily halted at any time, if the appropriate receive/transmit buffer is not ready (srdy = 0). the srdy status will then automatically be set back to ?1? and data shifting resumed as soon as the application software loads the new data into the transmit register (in tx mode) or frees the shift register by reading it into the receive buffer (in rx mode). a further activity status (act) bit indicates the present status of serial communication. the act bit remains high for the duration of the serial telegram or if mcl stop or start conditions are cur- rently being generated. both the current srdy and act status can be read in the ssi status register. to deactivate the ssi, the sir bit must be set high.
44 4708d?4bmcu?09/05 ata6020n 5.2.7.4 8-bit synchronous mode figure 5-24. 8-bit synchronous mode in the 8-bit synchronous mode, the ssi can operate as either a 2- or 3-wire interface (see sec- tion ?ssi peripheral configuration? on page 42 ). the serial data (sd) is received or transmitted in nrz format, synchronized to either the rising or falling edge of the shift clock (sc). the choice of clock edge is defined by the serial mode control bits (sm0, sm1). it should be noted that the transmission edge refers to the sc clock edge with which the sd changes. to avoid clock skew problems, the incoming serial input data is shifted in with the opposite edge. when used together with one of the timer modulator or demodulator stages, the ssi must be set in the 8-bit synchronous mode 1. in rx mode, as soon as the ssi is activated (s ir = 0), 8 shift clocks are generated and the incoming serial data is shifted into the shift register. this first telegram is automatically trans- ferred into the receive buffer and the srdy flag is set to 0 indicating that the receive buffer contains valid data. at the same time an interrupt (if enabled) is generated. the ssi then contin- ues shifting in the following 8-bit telegram. if, during this time the first telegram has been read by the controller, the second telegram will also be transferre d in the same way into the receive buffer and the ssi will continue clocking in the next telegram. should, however, the first tele- gram not have been read (srdy = 1), then the ssi will stop, temporarily holding the second telegram in the shift register until a certain point in time when the controller is able to service the receive buffer. in this way no data is lost or overwritten. deactivating the ssi (sir = 1) in mid-telegram will immediately st op the shift clock and latch the present contents of the shift register into the receive buffer. this can be used for clocking in a data telegram of less than 8 bits in length. care should be taken to read out the final complete 8-bit data telegram of a multiple word message before deactivating the ssi (sir = 1) and termi- nating the reception. after termination, the sh ift register contents will overwrite the receive buffer. sc sc data sd/to2 110 101 00 bit 7 bit 0 110 101 00 bit 7 bit 0 data: 00110101 (rising edge) (falling edge)
45 4708d?4bmcu?09/05 ata6020n figure 5-25. example of 8-bit synchronous transmit operation figure 5-26. example of 8-bit synchronous receive operation 5.2.7.5 9-bit shift mode in the 9-bit shift mode, the ssi is able to handle the mcl protocol (described below). it always operates as an mcl master device, i.e., sc is always generated and output by the ssi. both the mcl start and stop conditions are automatically generated whenever the ssi is activated or deactivated by the sir-bit. in accordance with the mcl protocol, the output data is always changed in the clock low phase and shifted in on the high phase. before activating the ssi (sir = 0) and commencing an mcl dialog, the appropriate data direc- tion for the first word must be set using the sdd control bit. the state of this bit controls the direction of the data port (bp43 or mcl_sd). once started, the 8 data bits are, depending on the selected direction, either clocked into or out of the shift register. during the 9th clock period, the port direction is automatically switched over so that the correspond ing acknowledge bit can be shifted out or read in. in transmit mode, the acknowledge bit received from the device is cap- tured in the ssi status register (tack) where it can be read by the controller. a receive mode, the state of the acknowledge bit to be returned to the device is predetermined by the ssi status register (rack). 7654321 0 765432107654321 0 msb lsb tx data 1 tx data 2 tx data 3 msb lsb msb lsb write stb (tx data 2) write stb (tx data 3) write stb (tx data 1) sc sd sir srdy interrupt (ifn = 0) interrupt (ifn = 1) act 43210 76543210 msb lsb rx data 1 rx data 2 rx data 3 msb lsb msb lsb read srb (rx data 2) read srb (rx data 3) read srb (rx data 1) sc sd sir srdy interrupt (ifn = 0) interrupt (ifn = 1) act 765 43210 765 7654
46 4708d?4bmcu?09/05 ata6020n changing the directional mode (tx/rx) should not be performed during the transfer of an mcl telegram. one should wait until the end of the telegram which can be detected using the ssi interrupt (ifn = 1) or by interrogating the act status. a 9-bit telegram, once started will always run to completion and will not be prematurely termi- nated by the sir bit. so, if the sir-bit is set to ?1? in with telegram, the ssi will complete the current transfer and terminate the dialog with an mcl stop condition. figure 5-27. example of mcl transmit dialog figure 5-28. example of mcl receive dialog 7654321 76543210a msb lsb tx data 1 tx data 2 msb lsb write stb (tx data 1) sc sd srdy act interrupt (ifn = 0) interrupt (ifn = 1) 0a write stb (tx data 2) sir sdd start stop 7654321 76543210 a msb lsb tx data 1 rx data 2 msb lsb write stb (tx data 1) sc sd srdy act interrupt (ifn = 0) interrupt (ifn = 1) 0a read srb (rx data 2) sir sdd start stop
47 4708d?4bmcu?09/05 ata6020n 5.2.7.6 8-bit pseudo mcl mode in this mode, the ssi exhibits all the typical mcl operational features except for the acknowl- edge-bit which is never expected or transmitted. 5.2.7.7 mcl bus protocol the mcl protocol constitutes a simple 2-wire bi-directional communica tion highway via which devices can communicate control and data information. although the mcl protocol can support multi-master bus configurations, the ssi, in mcl mode is intended for use purely as a master controller on a single master bus system. so all reference to multiple bus control and bus con- tention will be omi tted at this point. all data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit. nor- mally the communication channel is opened with a so-called start condition, which initializes all devices connected to the bus. this is then follo wed by a data telegram, transmitted by the mas- ter controller device. this telegram usually co ntains an 8-bit address code to activate a single slave device connected onto the mcl bus. each slave receives this address and compares it with its own unique address. the addressed slave device, if ready to receive data will respond by pulling the sd line low during the 9th clock pu lse. this represents a so-called mcl acknowl- edge. the controller on detecting this affirmative acknowledge then opens a connection to the required slave. data can then be passed back and forth by the master controller, each 8-bit tele- gram being acknowledged by the respective reci pient. the communication is finally closed by the master device and the slave device put back into standby by applying a stop condition onto the bus. figure 5-29. mcl bus protocol 1 bus not busy (1) both data and clock lines remain high. start data transfer (2) a high to low transition of the sd line while the clock (sc) is high defines a start condition. stop data transfer (3) a low to high transition of the sd line while the clock (sc) is high defines a stop condition. data valid (4) the state of the data line represents valid data when, after start condition, the data line is stable for the duration of the high period of the clock signal. (2) (1) (4) (4) (3) (1) start condition data valid data change data valid stop condition sc sd
48 4708d?4bmcu?09/05 ata6020n acknowledge all address and data words are serially transmitted to and from the device in eight-bit words. the receiving device returns a zero on the data line during the ninth clock cycle to acknowledge word receipt. figure 5-30. mcl bus protocol 2 5.2.7.8 ssi interrupt the ssi interrupt int3 can be generated either by an ssi buffer register status (i.e., transmit buffer empty or receive buffer full) at the end of an ssi data telegram or on the falling edge of the sc/sd pins on port 4 (see p4cr). ssi interrupt selection is performed by the interrupt function control bit (ifn). the ssi interrupt is usually used to synchronize the software control of the ssi and inform the controller of the present ssi status. port 4 interrupts can be used together with the ssi or, if the ssi itself is not required, as additional external interrupt sources. in either case this interrupt is capable of waking the controller out of sleep mode. to enable and select the ssi relevant interrupts use the ssi interrupt mask (sim) and the inter- rupt function (ifn) while port 4 interrupts are enabled by setting appropriate control bits in p4cr register. 5.2.7.9 modulation if the shift register is used together with timer 2 for modulation purposes, the 8-bit synchronous mode must be used. in this case, the unused port 4 pins can be used as conventional bi-direc- tional ports. the modulation stage, if enabled, operates as soon as the ssi is activated (sir = 0) and ceases when deactivated (sir = 1). due to the byte-orientated data control, the ssi (when running normally) generates serial bit- streams which are submultiples of 8 bits. however, an ssi output masking (omsk) function per- mits, however, the generation of bit-streams of any length. the omsk signal is derived indirectly from the 4-bit prescaler of the timer 2 and masks out a programmable number of unrequired trailing data bits during the shifting out of the final data word in the bit stream. the number of non-masked data bits is defined by the value pre-programmed in the prescaler compare register. to use output masking, the modulator stop mode bit (msm) must be set to ?0? before program- ming the final data word into th e ssi transmit buffer. this in turn, enables shift clocks to the prescaler when this final word is shifted out. on reaching the compare value, the prescaler trig- gers the omsk signal and all following data bits are blanked. sc sd start 1n89 1st bit 8th bit ack stop
49 4708d?4bmcu?09/05 ata6020n figure 5-31. ssi output masking function 5.2.7.10 serial interface registers 5.2.7.11 serial interface control register 1 (sic1) 8-bit shift register msb lsb shift_cl so control si timer 2 output ssi-control so compare 2/1 4-bit counter 2/1 cl2/1 scl cm1 omsk sc tog2 pout t1out syscl /2 auxiliary register address: ?9?hex bit 3 bit 2 bit 1 bit 0 sic1 sir scd scs1 scs0 reset value: 1111b sir s erial i nterface r eset sir = 1, ssi inactive sir = 0, ssi active scd s erial c lock d irection scd = 1, sc line used as output scd = 0, sc line used as input note: this bit has to be set to '1' during the mcl mode scs1 s erial c lock source s elect bit 1 scs0 s erial c lock source s elect bit 0 note: with scd = '0' the bits scs1 and scs0 are insignificant table 5-12. serial clock source select bits scs1 scs0 internal clock for ssi 1 1 syscl/2 10t1out/2 01pout/2 00tog2/2
50 4708d?4bmcu?09/05 ata6020n in transmit mode (sdd = 1) shifting starts only if the transmit buffer has been loaded (srdy = 1). setting sir-bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only). in mcl modes, writing a 0 to sir generates a start condition and writing a 1 generates a stop condition. 5.2.7.12 serial interface control register 2 (sic2) sdd controls port directional control and defines the reset function for the srdy-flag auxiliary register address: ?a?hex bit 3 bit 2 bit 1 bit 0 sic2 msm sm1 sm0 sdd reset value: 1111b msm m odular s top m ode msm = 1, modulator stop mode disabled (output masking off) msm = 0, modulator stop mode enabled (output masking on) - used in modulation modes for generating bit streams which are not sub?multiples of 8 bit. sm1 s erial m ode control bit 1 sm0 s erial m ode control bit 0 table 5-13. serial mode control bits mode sm1 sm0 ssi mode 1 1 1 8-bit nrz-data changes with the rising edge of sc 2 1 0 8-bit nrz-data changes with the falling edge of sc 3 0 1 9-bit two-wire mcl compatible 4 0 0 8-bit two-wire pseudo mcl compatible (no acknowledge) sdd s erial d ata d irection sdd = 1, transmit mode - sd line used as output (transmit data). srdy is set by a transmit buffer write access sdd = 0, receive mode - sd line used as input (receive data). srdy is set by a receive buffer read access
51 4708d?4bmcu?09/05 ata6020n 5.2.7.13 serial interface status and control register (sisc) 5.2.7.14 serial transmit buffer (stb) ? byte write the stb is the transmit buffer of the ssi. the ssi transfers the transmit buffer into the shift reg- ister and starts shifting with the most significant bit. 5.2.7.15 serial receive buffer (srb) ? byte read the srb is the receive buffer of the ssi. the shift register clocks serial da ta in (most significant bit first) and loads content into the receive buffer when complete telegram has been received. primary register address: ?a?hex bit 3 bit 2 bit 1 bit 0 sisc write rack sim ifn reset value: 1111b sisc read ? tack act srdy reset value: xxxxb rack r eceive ack nowledge status/control bit for mcl mode rack = 0, transmit acknowledge in next receive telegram rack = 1, transmit no acknowledge in last receive telegram tack t ransmit ack nowledge status/control bit for mcl mode tack = 0, acknowledge received in last transmit telegram tack = 1, no acknowledge received in last transmit telegram sim s erial i nterrupt m ask sim = 1, disable interrupts sim = 0, enable serial interrupt. an interrupt is generated. ifn i nterrupt f u n ction ifn = 1, the serial interrupt is generated at the end of the telegram ifn = 0, the serial interrupt is generated when the srdy goes low (i.e., buffer becomes empty/full in transmit/receive mode) srdy s erial interface buffer r ea dy status flag srdy = 1, in receive mode: receive buffer empty in transmit mode: transmit buffer full srdy = 0, in receive mode: receive buffer full in transmit mode: transmit buffer empty act transmission act ive status flag act = 1, transmission is active, i.e., serial data transfer. stop or start conditions are currently in progress. act = 0, transmission is inactive primary register address: ?9?hex stb first write cycle bit 3 bit 2 bit 1 bit 0 reset value: xxxxb second write cycle bit 7 bit 6 bit 5 bit 4 reset value: xxxxb primary register address: ?9?hex srb first read cycle bit 7 bit 6 bit 5 bit 4 reset value: xxxxb second read cycle bit 3 bit 2 bit 1 bit 0 reset value: xxxxb
52 4708d?4bmcu?09/05 ata6020n 5.2.8 combination modes the utcm consists of one timer (timer 2) and a serial interface. there is a multitude of modes in which the timers and serial interface can work together. the 8-bit wide serial interface oper- ates as shift register for modulation. the modulato r units work together with the timers and shift the data bits into or out of the shift register. 5.2.8.1 combination mode timer 2 and ssi figure 5-32. combination timer 2 and ssi 4-bit counter 2/1 res ovf1 compare 2/1 t2co1 pout cl2/2 dcg t2m1 p4cr 8-bit counter 2/2 res ovf2 compare 2/2 t2co2 t2cm timer 2 - control tog2 int4 bi-phase manchester modulator output mout t2o timer 2 modulator output-stage t2m2 so control t2c cl2/1 t2i syscl t1out reserved scl i/o-bus 8-bit shift register msb lsb shift_cl so sic1 sic2 sisc scli control stb srb si output int3 i/o-bus ssi-control tog2 pout t1out syscl transmit buffer receive buffer cm1 i/o-bus pout so scl sc sd dcgo tog2
53 4708d?4bmcu?09/05 ata6020n combination mode 1 burst modulation ssi mode 1: 8-bit nrz and internal data so output to the timer 2 modulator stage timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler and dcg timer 2 output mode 3: duty cycle burst generator figure 5-33. carrier frequency burst modulation with the ssi internal data output combination mode 2: bi-phase modulation 1 ssi mode 1: 8-bit shift register internal data output (so) to the timer 2 modulator stage timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler timer 2 output mode 4: the modulator 2 of timer 2 modulates the ssi internal data out put to bi-phase code figure 5-34. bi-phase modulation 1 1 201201201201201201201201201201201201201 dcgo counter 2 tog2 so t2o counter = compare register (=2) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 tog2 sc so t2o 000 0 0011 0101 11 1 1 8-bit sr-data bit 7 bit 0 data: 00110101
54 4708d?4bmcu?09/05 ata6020n combination mode 3: manchester modulation 1 ssi mode 1: 8-bit shift register internal data output (so) to timer 2 modulator stage timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler timer 2 output mode 5: the modulator 2 of timer 2 modulates the ssi internal data out put to manchester code figure 5-35. manchester modulation 1 combination mode 4: manchester modulation 2 ssi mode 1: 8-bit shift register internal data output (so) to the timer 2 modulator stage timer 2 mode 3: 8-bit compare counter and 4-bit prescaler timer 2 output mode 5: the modulator 2 of timer 2 modulates the ssi data output to manchester code the 4-bit stage can be used as prescaler for the ssi to generate the stop signal for modulator 2. the ssi has a special mode to supply the prescaler with the shift-clock. the control output sig- nal (omsk) of the ssi is used as stop signal for the modulator. figure 5-36 is an example for a 12-bit manchester telegram. figure 5-36. manchester modulation 2 tog2 sc so t2o 00 0 0011 0101 11 1 1 8-bit sr-data bit 7 bit 0 0 bit 7 bit 0 data: 00110101 00000000 123 4 012 0 counter 2/1 = compare register 2/1 (= 4) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scli buffer full sir so sc msm timer 2 mode 3 scl counter 2/1 omsk t2o 3
55 4708d?4bmcu?09/05 ata6020n combination mode 5: bi-phase modulation 2 ssi mode 1: 8-bit shift register internal data output (so) to timer 2 modulator stage timer 2 mode 3: 8-bit compare counter and 4-bit prescaler timer 2 output mode 4: the modulator 2 of timer 2 modulates the ssi data output to bi-phase code the 4-bit stage can be used as prescaler for the ssi to generate the stop signal for modulator 2. the ssi has a special mode to supply the prescaler via the shift-clock. the control output signal (omsk) of the ssi is used as a stop signal for the modulator. figure 5-37 is an example for a 13-bit bi-phase telegram. figure 5-37. bi-phase modulation 00000000 1234 5 0 counter 2/1 = compare register 2/1 (= 5) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scli buffer full sir so sc msm timer 2 mode 3 scl 2/1 omsk t2o 012
56 4708d?4bmcu?09/05 ata6020n 6. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . all inputs and outputs are protected against high electrostatic vo ltages or electric fields. however, precautions to minimize t he build-up of electrostatic charges during handling are recommended. reliabilit y of operation is enhanced if unused inputs are connected to a n appropriate logic voltage level (e.g., v dd ). voltages are given relative to v ss parameters symbol value unit supply voltage v dd ?0.3 to +6.5 v input voltage (on any pin) v in v ss ?0.3 v in v dd +0.3 v output short circuit duration t short indefinite s operating temperature range t amb ?40 to +85 c storage temperature range t stg ?40 to +130 c thermal resistance (sso20) r thja 140 k/w soldering temperature (t 10s) t sld 260 c 7. operating characteristics v dd = 5v, v ss = 0v, t amb = ?40c to +85c unless otherwise specified parameters test conditions symbol min. typ. max. unit power supply active current cpu active r ext = 47 k ? f syscl = f rcext /2 f syscl = f rcext /4 i dd 330 170 370 190 a a power down current (cpu sleep, rc-oscillator active) r ext = 47 k ? f syscl = f rcext /2 f syscl = f rcext /4 f syscl = f rcext /16 i pd 40 35 30 45 40 35 a a a sleep current (cpu sleep, rc-oscillator inactive) v dd = 6.5v i sleep 0.5 0.8 a v dd = 5.5v, v ss = 0v, t amb = ?40c to +85c unless otherwise specified. parameters test conditions symbol min. typ. max. unit active current cpu active r ext = 47 k ? f syscl = f rcext /2 f syscl = f rcext /4 idd 370 190 410 210 a a power down current (cpu sleep, rc oscillator active) r ext = 47 k ? f syscl = f rcext /2 f syscl = f rcext /4 f syscl = f rcext /16 ipd 45 40 35 50 45 40 a a a
57 4708d?4bmcu?09/05 ata6020n 7.1 all bi-directional ports note: the pin bp20/nte has a static pull-up resistor during the reset-phase of the microcontroller: v ss = 0v, t amb = 25c unless otherwise specified. parameters test conditions symbol min. typ. max. unit power-on reset threshold voltage por threshold voltage bot = 1 v por 2.5 3.0 3.5 v por threshold voltage bot = 0 v por 3.5 4.0 4.5 v por hysteresis v por 50 mv voltage monitor threshold voltage vm high threshold voltage v dd > vm, vms = 1 v mthh 5.0 5.5 v vm high threshold voltage v dd < vm, vms = 0 v mthh 4.5 5.0 v vm low threshold voltage v dd > vm, vms = 1 v mthl 4.0 4.5 v vm low threshold voltage v dd < vm, vms = 0 v mthl 3.5 4.0 v external input voltage vmi vmi > vbg, vms = 1 v vmi 1.25 1.4 v vmi vmi < vbg, vms = 0 v vmi 1.1 1.25 v v ss = 0v, t amb = ?40c to +85c unless otherwise specified. parameters test conditions symbol min. typ. max. unit input voltage low v dd = 3.5v to 6.5v v il v ss 0.2 v dd v input voltage high v dd = 3.5v to 6.5v v ih 0.8 v dd v dd v input low current (dynamic pull-up) v dd = 3.5v, v il = v ss v dd = 6.5v i il ?15 ?50 ?30 ?100 ?50 ?200 a a input high current (dynamic pull-down) v dd = 3.5v, v ih = v dd v dd = 6.5v i ih 15 50 30 100 50 200 a a input low current (static pull-up) v dd = 3.5v, v il = v ss v dd = 6.5v i il ?120 ?300 ?250 ?600 ?500 ?1200 a a input low current (static pull-down) v dd = 3.5v, v ih = v dd v dd = 6.5v i ih 120 300 250 600 500 1200 a a output low current v ol = 0.2v dd v dd = 3.5v, v dd = 6.5v i ol 3 8 5 15 8 22 ma ma output high current v oh = 0.8v dd v dd = 3.5v, v dd = 6.5v i oh ?3 ?8 ?5 ?16 ?8 ?24 ma ma
58 4708d?4bmcu?09/05 ata6020n 8. ac characteristics 8.1 operation cycle time v ss = 0v parameters test conditions symbol min. typ. max. unit system clock cycle v dd = 2.5v to 6.5v t amb = ?40 c to +85 c t syscl 0.25 100 s supply voltage v dd = 2.5v to 6.5v, v ss = 0v, t amb = 25c unless otherwise specified. parameters test conditions symbol min. typ. max. unit timer 2 input timing pin t2i timer 2 input clock f t2i 5mhz timer 2 input low time rise/fall time < 10 ns t t2il 100 ns timer 2 input high time rise/fall time < 10 ns t t2ih 100 ns interrupt request input timing interrupt request low time rise/fall time < 10 ns t irl 100 ns interrupt request high time rise/fall time < 10 ns t irh 100 ns external system clock exscl at osc1 input ecm = en rise/fall time < 10 ns f exscl 0.5 8 mhz exscl at osc1 input ecm = di rise/fall time < 10 ns f exscl 0.02 8 mhz input high time rise/fall time < 10 ns t ih 0.1 s reset timing power-on reset time v dd >v por t por 1.5 5 ms rc-oscillator 1 frequency f rcout1 4mhz stability v dd = 3.5v to 5.5v t amb = ?40 c to +85 c ? f/f 50 % stabilization time v dd = 3.5v to 5.5v t s 1ms rc-oscillator 2 ? external resistor frequency r ext = 47 k ? f rcout2 1.6 mhz stability v dd = 3.5v to 5.5v t amb = ?40 c to +85 c ? f/f 10 % stabilization time v dd = 3.5v to 5.5v t s 1ms external resistor r ext 12 47 100 k ?
59 4708d?4bmcu?09/05 ata6020n figure 8-1. active supply current versus frequency figure 8-2. power-down supply current versus frequency figure 8-3. active supply current versus v dd 0.000 0.200 0.400 0.600 0.800 1.000 1.200 1.400 1.600 1.800 2.000 0 500 1000 1500 2000 2500 3000 3500 4000 system clock (khz) i ddact (ma) t amb = 25c v dd = 6.5 v 5 v 3 v 2 v 0 50 100 150 200 250 200 400 600 800 1000 1200 1400 1600 1800 2000 system clock (khz) i pd (a) v dd = 6.5 v 5 v 4 v 3 v 2 v t amb = 25c 0.000 0.100 0.200 0.300 0.400 0.500 0.600 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd (v) i ddact (ma) f sysclk = 1 mhz t amb = 85c 25c -40c
60 4708d?4bmcu?09/05 ata6020n figure 8-4. power-down supply current versus v dd figure 8-5. internal rc frequency versus v dd figure 8-6. external rc frequency versus v dd 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd (v) i pd (a) f syscl = 500 khz t amb = 25c 2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 5.00 5.20 5.40 5.60 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd (v) f rc_int (mhz) t amb = -40c 25c 85c 1.570 1.590 1.610 1.630 1.650 1.670 1.690 1.710 1.730 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd (v) f rc_ext (mhz) r ext = 43k t amb = -40c 25c 85c
61 4708d?4bmcu?09/05 ata6020n figure 8-7. maximum system clock versus v dd figure 8-8. internal rc frequency versus t amb figure 8-9. external rc frequency versus t amb 0.00 2.00 4.00 6.00 8.00 10.00 12.00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd (v) f sysclk (mhz) 2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 5.00 5.20 5.40 5.60 -40-30-20-10 0 102030 40 5060 708090 t amb (c) f rc_int (mhz) v dd = 6.5 v 2 v 3 v 1.570 1.590 1.610 1.630 1.650 1.670 1.690 1.710 1.730 -40-30-20-100 10203040 5060 708090 t amb (c) f rc_ext (mhz) 2 v v dd = 6.5 v 3 v r ext = 43k
62 4708d?4bmcu?09/05 ata6020n figure 8-10. external rc frequency versus r ext figure 8-11. pull-up resistor versus v dd figure 8-12. strong pull-up re sistor versus v dd 500 1500 2500 3500 4500 5500 10 20 30 40 50 60 70 80 90 100 110 r ext (k ? ) f rc_ext (khz) v dd = 5 v t amb = 25c max min typ. 10.0 100.0 1000.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd (v) r pu (k ? ) t amb = 85c v il = v ss -40c 25c 10.0 100.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd (v) r spu (k ? ) v il = v ss t amb = 85c -40c 25c
63 4708d?4bmcu?09/05 ata6020n figure 8-13. output high current versus v dd - output high voltage figure 8-14. pull-down resistor versus v dd figure 8-15. strong pull-down resistor versus v dd -40.0 -35.0 -30.0 -25.0 -20.0 -15.0 -10.0 -5.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd - v oh (v) i oh (ma) t amb = 25c v dd = 2.0 v 4.0 v 3.0 v 5.0 v 6.5 v 10 100 1000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd (v) r pd (k ? ) v ih = v dd t amb = 85c -40c 25c 10.0 100.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd (v) r spd (k ? ) v ih = v dd t amb = 85c 25c -40c
64 4708d?4bmcu?09/05 ata6020n figure 8-16. output low current versus output low voltage figure 8-17. output high current versus t amb = 25c, v dd = 6.5v, v oh = 0.8 v dd figure 8-18. output low current versus t amb , v dd = 6.5v, v ol = 0.2 v dd 0 5 10 15 20 25 30 0.00.51.01.52.02.53.03.54.04.55.05.56.06.5 v ol (v) i ol (ma) t amb = 25c v dd = 6.5 v 5 v 4 v 3 v 2 v -25 -20 -15 -10 -5 0 -40-30-20-10 0 102030 40 5060 7080 90 t amb (c) i oh (ma) max. typ. min. 0 5 10 15 20 25 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 t amb (c) i ol (ma) max. typ. min.
65 4708d?4bmcu?09/05 ata6020n 8.2 emulation the basic function of emulation is to test and evaluate the customer's program and hardware in real time. this therefore enables the analysis of any timing, hardware or software problem. for emulation purposes, all marc4 controllers includ e a special emulation mode. in this mode, the internal cpu core is inactive and the i/o buses are available via port 0 and port 1 to allow an external access to the on-chip peripherals. the marc4 emulator uses this mode to control the peripherals of any marc4 controller (target chip) and emulates the lost ports for the application. the marc4 emulator can stop and restart a program at specified points during execution, mak- ing it possible for the applications engineer to vi ew the memory contents and those of various registers during program execution. the designer also gains the ability to analyze the executed instruction sequences and all the i/o activities. figure 8-19. marc4 emulation marc4 target chip core (inactive) p o r t 1 p o r t 0 application-specific hardware peripherals marc4 emulator program memory trace memory control logic personal computer core marc4 emulation-cpu i/o control i/o bus port 0 port 1 syscl/ tcl, te, nrst emulation control emulator target board
66 4708d?4bmcu?09/05 ata6020n please attach this page to the approval form. date: ____________ signature: _________________________ company: _________________________ 9. option settings for ordering please select the option settings fr om the list below and insert rom crc. output input output input port 2 port 5 bp20 [ ] cmos [ ] pull-up bp50 [ ] cmos [ ] pull-up [ ] open drain [n] [ ] pull-down [ ] open drain [n] [ ] pull-down [ ] open drain [p] [ ] pull-up static [ ] open drain [p] [ ] pull-up static pull-down static [ ] pull-down static bp21 [ ] cmos [ ] pull-up bp51 [ ] cmos [ ] pull-up [ ] open drain [n] [ ] pull-down [ ] open drain [n] [ ] pull-down [ ] open drain [p] [ ] pull-up static [ ] open drain [p] [ ] pull-up static [ ] pull-down static [ ] pull-down static port 4 bp52 [ ] cmos [ ] pull-up bp40 [ ] cmos [ ] pull-up [ ] open drain [n] [ ] pull-down [ ] open drain [n] [ ] pull-down [ ] open drain [p] [ ] pull-up static [ ] open drain [p] [ ] pull-up static [ ] pull-down static [ ] pull-down static bp53 [ ] cmos [ ] pull-up bp41 [ ] cmos [ ] pull-up [ ] open drain [n] [ ] pull-down [ ] open drain [n] [ ] pull-down [ ] open drain [p] [ ] pull-up static [ ] open drain [p] [ ] pull-up static [ ] pull-down static [ ] pull-down static ecm (external clock monitor) bp42 [ ] cmos [ ] pull-up [ ] enable [ ] open drain [n] [ ] pull-down [ ] disable [ ] open drain [p] [ ] pull-up static watchdog [ ] pull-down static [ ] softlock bp43 [ ] cmos [ ] pull-up [ ] hardlock [ ] open drain [n] [ ] pull-down used oscillator [ ] open drain [p] [ ] pull-up static [ ] ext. rc [ ] pull-down static [ ] ext. clock
67 4708d?4bmcu?09/05 ata6020n 11. package information 10. ordering information extended type number (1) program memory data-eeprom package delivery ATA6020X-YYY-TKQY 2 kb rom no sso20, pb-free taped and reeled note: 1. x = hardware revision yyy = customer specific rom-version technical drawings according to din specifications package sso20 dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 110
68 4708d?4bmcu?09/05 ata6020n 12. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4708d-4bmcu-09/05 ? put datasheet in a new template ? pb-free logo on page 1 added ? ordering information on page 67 changed 4708c-4bmcu-02/04 ? figure 4 ?rom map? on page 4 changed. ? figure 55 to figure 72 on page 56 to page 61 added. 4708b-4bmcu-12/03 ? put datasheet in a new template. ? figure 5 ?ram map? on page 4 changed. ? table 9 ?peripheral addresses? on page 19 changed. ? new heading rows at table ?absolute maximum ratings? on page 53 added. ? section ?emulation? on page 56 added. ? table ?ordering information? on page 58 added. ? table name on page 57 changed.
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